High-density memory cells, such as ferroelectric memory (FRAM) cells, can used in arrays of ferroelectric capacitors fabricated as part of a complementary metal-oxide-semiconductor (CMOS) transistor process flow. The material layers of the capacitors are often fabricated by standard lithographic and etch processes which include the use of organic bottom antireflective coating (BARC) and hardmask (HM) layers formed on the material layers. Patterned BARC and HM layers are used to define the dimensions of the capacitor in a subsequent etch process performed on the material layers.
In such cases, the time required to etch the HM layer in batchs of substrates can be variable, which in turn, can cause variations in the dimensions of the etched HM layer. Variations in the dimensions of the etched HM layer, in turn, can cause undesirable variations in the dimensions of the capacitors. The fabrications of large numbers of capacitors having dimensions that are outside the range of a target dimension results in lower-than-desired yields of FRAM cells.